A buffer circuit having an output node (V o), a Darlington transistor pair (Q2, Q3) comprising first and second stage pullup transistors with an emitter node of the first stage pullup transistor (Q2) coupled to the base node of the second stage pullup transistor (Q3) for sourcing current from a high potential power rail (V cc) to the output node, a pulldown transistor (Q4) coupled for sinking current from the output node to a low potential power rail (GND), an anti-simultaneous transistor (Q5) having a collector node coupled to a base node of said Darlington transistor pair, and an emitter node directly connected to said low potential power rail (GND), and a ballast resistor network (R6, R7) coupled between the base node of the anti-simultaneous transistor and the base node of the pulldown transistor, characterized in that said collector node of said anti-simultaneous transistor (Q5) is coupled to the base node of said second stage pullup transistor (Q3) and to the emitter node of said first stage pullup transistor (Q2) for sinking current from the base node of said second stage pullup transistor (Q3).Ģ.
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